AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 139
AT89C51SND2C-7FTUL
Manufacturer Part Number
AT89C51SND2C-7FTUL
Description
IC 8051 MCU FLASH 64K MP3 100BGA
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C51SND2C-7FTUL.pdf
(242 pages)
Specifications of AT89C51SND2C-7FTUL
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
Peripherals
Audio, I²S, MP3, PCM, POR, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 2x10b; D/A 2x20b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Data Bus Width
8 bit
Data Ram Size
2.25 KB
Interface Type
ATAPI, I2S, IDE, SPI, UART, USB
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
AT89C51SND2C7FTUL
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18.2.6
18.3
4341H–MP3–10/07
Description
Clock Control
Figure 18-8. Data Token Format
The MMC bus clock signal can be used by the host to turn the cards into energy saving mode or
to control the data flow (to avoid under-run or over-run conditions) on the bus. The host is
allowed to lower the clock frequency or shut it down.
There are a few restrictions the host must follow:
•
•
•
•
•
•
•
The MMC controller interfaces to the C51 core through the following eight special function
registers:
MMCON0, MMCON1, MMCON2, the three MMC control registers (see Table 18-8 to
16); MMSTA, the MMC status register (see Table 18-11); MMINT, the MMC interrupt register
(see Table 18-12); MMMSK, the MMC interrupt mask register (see Table 18-13); MMCMD, the
MMC command register (see Table 18-14); MMDAT, the MMC data register (see Table 18-15);
and MMCLK, the MMC clock register (see Table 18-16).
As shown in Figure 18-9, the MMC controller is divided in four blocks: the clock generator that
handles the MCLK (formally the MMC CLK) output to the card, the command line controller that
handles the MCMD (formally the MMC CMD) line traffic to or from the card, the data line control-
ler that handles the MDAT (formally the MMC DAT) line traffic to or from the card, and the
interrupt controller that handles the MMC controller interrupt sources. These blocks are detailed
in the following sections.
The bus frequency can be changed at any time (under the restrictions of maximum data
transfer frequency, defined by the cards, and the identification frequency defined by the
specification document).
It is an obvious requirement that the clock must be running for the card to output data or
response tokens. After the last MultiMedia Card bus transaction, the host is required, to
provide 8 (eight) clock cycles for the card to complete the operation before shutting down
the clock. Following is a list of the various bus transactions:
A command with no response. 8 clocks after the host command End bit.
A command with response. 8 clocks after the card command End bit.
A read data transaction. 8 clocks after the End bit of the last data block.
A write data transaction. 8 clocks after the CRC status token.
The host is allowed to shut down the clock of a “busy” card. The card will complete the
programming operation regardless of the host clock. However, the host must provide a clock
edge for the card to turn off its busy signal. Without a clock edge the card (unless previously
disconnected by a deselect command-CMD7) will force the MDAT line down, forever.
Sequential Data
Block Data
0
0
Block Length
Content
AT8xC51SND2C/MP3B
Content
CRC
1
1
Table 18-
139
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