AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 127

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

4341H–MP3–10/07
Table 16-9.
Reset Value = 0000 0000b
Table 16-10. UEPIEN Register
Reset Value = 0000 0000b
Bit Number
Bit Number
7 - 3
7 - 3
7
2
1
0
7
2
1
0
-
-
Mnemonic
Mnemonic
EP2INTE
EP1INTE
EP0INTE
EP2RST
EP1RST
EP0RST
UEPRST Register
UEPRST (S:D5h) – USB Endpoint FIFO Reset Register
UEPIEN (S:C2h) – USB Endpoint Interrupt Enable Register
Bit
Bit
6
6
-
-
-
-
Description
Reserved
The value read from these bits is always 0. Do not set these bits.
Endpoint 2 FIFO Reset
Set and clear to reset the endpoint 2 FIFO prior to any other operation, upon hardware
reset or when an USB bus reset has been received.
Endpoint 1 FIFO Reset
Set and clear to reset the endpoint 1 FIFO prior to any other operation, upon hardware
reset or when an USB bus reset has been received.
Endpoint 0 FIFO Reset
Set and clear to reset the endpoint 0 FIFO prior to any other operation, upon hardware
reset or when an USB bus reset has been received.
Description
Reserved
The value read from these bits is always 0. Do not set these bits.
Endpoint 2 Interrupt Enable Bit
Set to enable the interrupts for endpoint 2.
Clear this bit to disable the interrupts for endpoint 2.
Endpoint 1 Interrupt Enable Bit
Set to enable the interrupts for the endpoint 1.
Clear to disable the interrupts for the endpoint 1.
Endpoint 0 Interrupt Enable Bit
Set to enable the interrupts for the endpoint 0.
Clear to disable the interrupts for the endpoint 0.
5
5
-
-
4
4
-
-
AT8xC51SND2C/MP3B
3
3
-
-
EP2INTE
EP2RST
2
2
EP1INTE
EP1RST
1
1
EP0INTE
EP0RST
0
0
127