AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 112

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

16.6.3
112
AT8xC51SND2C/MP3B
Bulk/Interrupt IN Transactions in Standard Mode
If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data won’t be
stored, but the USB controller will consider that the packet is valid if the CRC is correct.
Figure 16-11. Bulk/Interrupt IN Transactions in Standard Mode
An endpoint should be first enabled and configured before being able to send Bulk or Interrupt
packets.
The firmware should fill the FIFO with the data to be sent and set the TXRDY bit in the UEP-
STAX register to allow the USB controller to send the data stored in FIFO at the next IN request
concerning this endpoint. To send a Zero Length Packet, the firmware should set the TXRDY bit
without writing any data into the endpoint FIFO.
Until the TXRDY bit has been set by the firmware, the USB controller will answer a NAK hand-
shake for each IN requests.
To cancel the sending of this packet, the firmware has to reset the TXRDY bit. The packet stored
in the endpoint FIFO is then cleared and a new packet can be written and sent.
When the IN packet has been sent and acknowledged by the Host, the TXCMPL bit in the UEP-
STAX register is set by the USB controller. This triggers a USB interrupt if enabled. The firmware
should clear the TXCMPL bit before filling the endpoint FIFO with new data.
The firmware should never write more Bytes than supported by the endpoint FIFO.
All USB retry mechanisms are automatically managed by the USB controller.
IN
IN
HOST
ACK
DATA0 (n Bytes)
NAK
UFI
TXCMPL
Endpoint FIFO Write Byte 1
Endpoint FIFO Write Byte 1
Endpoint FIFO Write Byte 2
Endpoint FIFO Write Byte n
Clear TXCMPL
Set TXRDY
C51
4341H–MP3–10/07