AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 191

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

Table 21-3.
4341H–MP3–10/07
SSSTA
Status
Code
08h
10h
38h
40h
48h
50h
58h
Status of the TWI Bus
and TWI Hardware
A START condition has
been transmitted
A repeated START
condition has been
transmitted
Arbitration lost in
SLA+R or NOT ACK
bit
SLA+R has been
transmitted; ACK has
been received
SLA+R has been
transmitted; NOT ACK
has been received
Data Byte has been
received; ACK has
been returned
Data Byte has been
received; NOT ACK
has been returned
Status for Master Receiver Mode
To/From SSDAT
Write SLA+R
Write SLA+R
Write SLA+W
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
Read data Byte
Read data Byte
Read data Byte
Read data Byte
Read data Byte
Application Software Response
SSSTA
X
X
X
0
1
0
0
1
0
1
0
0
1
0
1
SSSTO
To SSCON
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
SSI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSAA
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
AT8xC51SND2C/MP3B
Next Action Taken by TWI Hardware
SLA+R will be transmitted.
SLA+R will be transmitted.
SLA+W will be transmitted.
Logic will switch to master transmitter mode.
TWI bus will be released and not addressed slave
mode will be entered.
A START condition will be transmitted when the bus
becomes free.
Data Byte will be received and NOT ACK will be
returned.
Data Byte will be received and ACK will be returned.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Data Byte will be received and NOT ACK will be
returned.
Data Byte will be received and ACK will be returned.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
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