AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 122

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

16.12 Registers
122
AT8xC51SND2C/MP3B
Table 16-3.
Reset Value = 0000 0000b
Bit Number
USBE
7
7
6
5
4
3
2
1
0
SDRMWUP
Mnemonic
SUSPCLK
SUSPCLK
RMWUPE
FADDEN
USBCON Register
USBCON (S:BCh) – USB Global Control Register
UPRSM
CONFG
USBE
Bit
6
-
Description
USB Enable Bit
Set this bit to enable the USB controller.
Clear this bit to disable and reset the USB controller, to disable the USB transceiver an
to disable the USB controllor clock inputs.
Suspend USB Clock Bit
Set to disable the 48 MHz clock input (Resume Detection is still active).
Clear to enable the 48 MHz clock input.
Send Remote Wake-Up Bit
Set to force an external interrupt on the USB controller for Remote Wake UP purpose.
An upstream resume is send only if the bit RMWUPE is set, all USB clocks are enabled
AND the USB bus was in SUSPEND state for at least 5 ms. See UPRSM below.
Cleared by software.
Reserved
The value read from this bit is always 0. Do not set this bit.
Upstream Resume Bit (read only)
Set by hardware when SDRMWUP has been set and if RMWUPE is enabled.
Cleared by hardware after the upstream resume has been sent.
Remote Wake-Up Enable Bit
Set to enabled request an upstream resume signaling to the host.
Clear after the upstream resume has been indicated by RSMINPR.
Note: Do not set this bit if the host has not set the DEVICE_REMOTE_WAKEUP feature
for the device.
Configuration Bit
This bit should be set by the device firmware after a SET_CONFIGURATION request
with a non-zero value has been correctly processed.
It should be cleared by the device firmware when a SET_CONFIGURATION request
with a zero value is received. It is cleared by hardware on hardware reset or when an
USB reset is detected on the bus (SE0 state for at least 32 Full Speed bit times: typically
2.7 µs).
Function Address Enable Bit
This bit should be set by the device firmware after a successful status phase of a
SET_ADDRESS transaction.
It should not be cleared afterwards by the device firmware. It is cleared by hardware on
hardware reset or when an USB reset is received (see above). When this bit is cleared,
the default function address is used (0).
SDRMWUP
5
4
-
UPRSM
3
RMWUPE
2
CONFG
1
4341H–MP3–10/07
FADDEN
0