AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 120

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

16.11.2
120
AT8xC51SND2C/MP3B
USB Interrupt Control System
Table 16-2.
As shown in Figure 16-16, many events can produce a USB interrupt:
•
•
•
•
•
•
•
•
TXCMPL: Transmitted In Data
Host accept a In packet.
RXOUTB0: Received Out Data Bank 0
when an Out packet is accepted by the endpoint and stored in bank 0.
RXOUTB1: Received Out Data Bank 1 (only for Ping-pong endpoints)
126). This bit is set by hardware when an Out packet is accepted by the endpoint and stored
in bank 1.
RXSETUP: Received Setup
SETUP packet is accepted by the endpoint.
STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints)
This bit is set by hardware when a STALL handshake has been sent as requested by
STALLRQ, and is reset by hardware when a SETUP packet is received.
SOFINT: Start of Frame Interrupt
a USB start of frame packet has been received.
WUPCPU: Wake-Up CPU Interrupt
when a USB resume is detected on the USB bus, after a SUSPEND state.
SPINT: Suspend Interrupt
suspend is detected on the USB bus.
IPHUSB
0
0
1
1
Priority Levels
(Table 16-5 on page
(Table 1 on page
IPLUSB
(Table 1 on page
(Table 16-5 on page
0
1
0
1
(Table 16-5 on page
(Table 1 on page
126). This bit is set by hardware when an
123). This bit is set by hardware when a USB
126). This bit is set by hardware when the
123). This bit is set by hardware when
123). This bit is set by hardware
126). This bit is set by hardware
3..................Highest
USB Priority Level
0..................Lowest
(Table 1 on page
1
2
(Table 1 on page
4341H–MP3–10/07
126).