AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 197

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

4341H–MP3–10/07
Table 21-10. SSSTA Register
SSSTA (S:94h) – Synchronous Serial Status Register
Reset Value = F8h
Table 21-11. SSDAT Register
SSDAT (S:95h) – Synchronous Serial Data Register
Reset Value = 1111 1111b
Table 21-12. SSADR Register
SSADR (S:96h) – Synchronous Serial Address Register
Reset Value = 1111 1110b
Bit Number
Bit Number
Bit Number
SSC4
SSD7
SSA7
7:3
2:0
7:1
7:1
7
7
0
7
0
Mnemonic
Mnemonic
Mnemonic
SSC4:0
SSD7:1
SSA7:1
SSGC
SSC3
SSD6
SSD0
SSA6
Bit
Bit
Bit
6
0
6
6
Description
Synchronous Serial Status Code Bits 0 to 4
Refer to Table 21-2 to Table 21-6 for status description.
Always 0.
Description
Synchronous Serial Address bits 7 to 1 or Synchronous Serial Data Bits 7 to 1
Synchronous Serial Address bit 0 (R/W) or Synchronous Serial Data Bit 0
Description
Synchronous Serial Slave Address Bits 7 to 1
Synchronous Serial General Call Bit
Set to enable the general call address recognition.
Clear to disable the general call address recognition.
SSC2
SSD5
SSA5
5
5
5
SSC1
SSD4
SSA4
4
4
4
SSC0
SSD3
SSA3
AT8xC51SND2C/MP3B
3
3
3
SSD2
SSA2
2
0
2
2
SSD1
SSA1
1
0
1
1
SSGC
SSD0
0
0
0
0
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