AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 111

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

16.6.2
4341H–MP3–10/07
Bulk/Interrupt OUT Transactions in Ping-pong Mode
Figure 16-10. Bulk/Interrupt OUT Transactions in Ping-pong Mode
An endpoint should be first enabled and configured before being able to receive Bulk or Interrupt
packets.
When a valid OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by the
USB controller. This triggers an interrupt if enabled. The firmware has to select the correspond-
ing endpoint, store the number of data Bytes by reading the UBYCTX register. If the received
packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has
to be read.
When all the endpoint FIFO Bytes have been read, the firmware should clear the RXOUB0 bit to
allow the USB controller to accept the next OUT packet on the endpoint bank 0. This action
switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has been cleared by the firmware,
the USB controller will answer a NAK handshake for each OUT requests on the bank 0 endpoint
FIFO.
When a new valid OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is set by
the USB controller. This triggers an interrupt if enabled. The firmware empties the bank 1 end-
point FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has been cleared by the
firmware, the USB controller will answer a NAK handshake for each OUT requests on the bank 1
endpoint FIFO.
The RXOUTB0 and RXOUTB1 bits are, alternatively, set by the USB controller at each new valid
packet receipt.
The firmware has to clear one of these 2 bits after having read all the data FIFO to allow a new
valid packet to be stored in the corresponding bank.
A NAK handshake is sent by the USB controller only if the banks 0 and 1 has not been released
by the firmware.
OUT
OUT
OUT
HOST
DATA0 (n Bytes)
DATA1 (m Bytes)
DATA0 (p Bytes)
ACK
ACK
ACK
UFI
RXOUTB0
RXOUTB1
RXOUTB0
AT8xC51SND2C/MP3B
Endpoint FIFO bank 0 - Read Byte 1
Endpoint FIFO bank 0 - Read Byte 2
Endpoint FIFO bank 0 - Read Byte n
Endpoint FIFO bank 1 - Read Byte 1
Endpoint FIFO bank 1 - Read Byte 2
Endpoint FIFO bank 1 - Read Byte m
Endpoint FIFO bank 0 - Read Byte 1
Endpoint FIFO bank 0 - Read Byte 2
Endpoint FIFO bank 0 - Read Byte p
Clear RXOUTB0
Clear RXOUTB1
Clear RXOUTB0
C51
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