AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 196

IC 8051 MCU FLASH 64K MP3 100BGA

AT89C51SND2C-7FTUL

Manufacturer Part Number
AT89C51SND2C-7FTUL
Description
IC 8051 MCU FLASH 64K MP3 100BGA
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of AT89C51SND2C-7FTUL

Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
Peripherals
Audio, I²S, MP3, PCM, POR, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 2x10b; D/A 2x20b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Data Bus Width
8 bit
Data Ram Size
2.25 KB
Interface Type
ATAPI, I2S, IDE, SPI, UART, USB
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
AT89C51SND2C7FTUL

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Quantity
Price
Part Number:
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196
AT8xC51SND2C/MP3B
Table 21-9.
Reset Value = 0000 0000b
Bit Number
SSCR2
7
7
6
5
4
3
2
1
0
Mnemonic
SSCON Register
SSCON (S:93h) – Synchronous Serial Control Register
SSCR2
SSSTO
SSCR1
SSCR0
SSSTA
SSPE
SSPE
SSAA
SSI
Bit
6
Description
Synchronous Serial Control Rate Bit 2
Refer to Table 21-1 for rate description.
Synchronous Serial Peripheral Enable Bit
Set to enable the controller.
Clear to disable the controller.
Synchronous Serial Start Flag
Set to send a START condition on the bus.
Clear not to send a START condition on the bus.
Synchronous Serial Stop Flag
Set to send a STOP condition on the bus.
Clear not to send a STOP condition on the bus.
Synchronous Serial Interrupt Flag
Set by hardware when a serial interrupt is requested.
Must be cleared by software to acknowledge interrupt.
Synchronous Serial Assert Acknowledge Flag
Set to enable slave modes. Slave modes are entered when SLA or GCA (if SSGC set) is
recognized.
Clear to disable slave modes.
Master Receiver Mode in progress
Master Transmitter Mode in progress
Slave Receiver Mode in progress
Slave Transmitter Mode in progress
Synchronous Serial Control Rate Bit 1
Refer to Table 21-1 for rate description.
Synchronous Serial Control Rate Bit 0
Refer to Table 21-1 for rate description.
SSSTA
Clear to force a not acknowledge (high level on SDA).
Set to force an acknowledge (low level on SDA).
This bit has no specific effect when in master transmitter mode.
Clear to force a not acknowledge (high level on SDA).
Set to force an acknowledge (low level on SDA).
Clear to isolate slave from the bus after last data Byte transmission.
Set to enable slave mode.
5
SSSTO
4
SSI
3
SSAA
2
SSCR1
1
4341H–MP3–10/07
SSCR0
0

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