AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 50

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

10.4.1
10.4.2
Figure 10-3. Power-down Exit Waveform Using INT1:0
Figure 10-4. Power-down Exit Waveform Using KIN0
Note:
50
1. KIN0 can be high or low-level triggered.
AT8xC51SND2C/MP3B
Entering Power-down Mode
Exiting Power-down Mode
INT1:0
KIN0
OSC
OSC
1
To enter Power-down mode, set PD bit in PCON register. The AT8xC51SND2C enters the
Power-down mode upon execution of the instruction that sets PD bit. The instruction that sets
PD bit is the last instruction executed.
If V
restored to the normal operating level.
There are 2 ways to exit the Power-down mode:
1. Generate an enabled external interrupt.
Note:
2. Generate a reset.
Active phase
Active phase
DD
–
was reduced during the Power-down mode, do not exit Power-down mode until V
The AT8xC51SND2C provides capability to exit from Power-down using INT0, INT1,
and KIN0 inputs. In addition, using KIN input provides high or low level exit capability
(see section “Keyboard Interface”, page 204).
Hardware clears PD bit in PCON register which starts the oscillator and restores the
clocks to the CPU and peripherals. Using INTn input, execution resumes when the
input is released (see Figure 10-3) while using KINx input, execution resumes after
counting 1024 clock ensuring the oscillator is restarted properly (see Figure 10-4).
This behavior is necessary for decoding the key while it is still pressed. In both
cases, execution resumes with the interrupt service routine. Upon completion of the
interrupt service routine, program execution resumes with the instruction
immediately following the instruction that activated Power-down mode.
1. The external interrupt used to exit Power-down mode must be configured as level sensitive
2. Exit from power-down by external interrupt does not affect the SFRs nor the internal RAM
(
interrupt must be long enough to allow the oscillator to stabilize. The execution will only
resume when the interrupt is deasserted.
content.
INT0
and
Power-down Phase
Power-down
INT1
) and must be assigned the highest priority. In addition, the duration of the
1024 clock count
Oscillator Restart
Active phase
Active Phase
4341H–MP3–10/07
DD
is