AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 170

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

20.3.1
20.3.2
170
AT8xC51SND2C/MP3B
Transmission (Mode 0)
Reception (Mode 0)
Figure 20-3. Serial I/O Port Block Diagram (Mode 0)
To start a transmission mode 0, write to SCON register clearing bits SM0, SM1.
As shown in Figure 20-4, writing the Byte to transmit to SBUF register starts the transmission.
Hardware shifts the LSB (D0) onto the RXD pin during the first clock cycle composed of a high
level then low level signal on TXD. During the eighth clock cycle the MSB (D7) is on the RXD
pin. Then, hardware drives the RXD pin high and asserts TI to indicate the end of the
transmission.
Figure 20-4. Transmission Waveforms (Mode 0)
To start a reception in mode 0, write to SCON register clearing SM0, SM1 and RI bits and setting
the REN bit.
As shown in Figure 20-5, Clock is pulsed and the LSB (D0) is sampled on the RXD pin. The D0
bit is then shifted into the shift register. After eight samplings, the MSB (D7) is shifted into the
shift register, and hardware asserts RI bit to indicate a completed reception. Software can then
read the received Byte from SBUF register.
Figure 20-5. Reception Waveforms (Mode 0)
Write to SCON
Write to SBUF
SCON.6
SCON.1
M3 M2 M1 M0
SM1
Mode Decoder
TI
Controller
RXD
RXD
TXD
TXD
Mode
RI
TI
SCON.7
SCON.0
SM0
RI
Set REN, Clear RI
D0
D0
D1
D1
CLOCK
CLOCK
BRG
PER
D2
D2
D3
D3
SBUF Rx SR
SBUF Tx SR
Baud Rate
Controller
D4
D4
D5
D5
D6
D6
D7
D7
4341H–MP3–10/07
RXD
TXD