EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 135

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13.4 Register Map
13.5 Register Description
13.5.1 PRS_SWPULSE - Software Pulse Register
31:8
7
6
5
4
3
2
1
0
Offset
0x000
0x004
0x008
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
Offset
0x000
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
The offset register address is relative to the registers base address.
Reserved
CH7PULSE
See bit 0.
CH6PULSE
See bit 0.
CH5PULSE
See bit 0.
CH4PULSE
See bit 0.
CH3PULSE
See bit 0.
CH2PULSE
See bit 0.
CH1PULSE
See bit 0.
CH0PULSE
Write to 1 to generate one HFPERCLK cycle high pulse. This pulse is XOR'ed with the corresponding bit in the SWLEVEL register
and the selected PRS input signal to generate the channel output.
Name
Name
PRS_SWPULSE
PRS_SWLEVEL
PRS_ROUTE
PRS_CH0_CTRL
PRS_CH1_CTRL
PRS_CH2_CTRL
PRS_CH3_CTRL
PRS_CH4_CTRL
PRS_CH5_CTRL
PRS_CH6_CTRL
PRS_CH7_CTRL
0
0
0
0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
W1
W1
W1
W1
W1
W1
W1
W1
Access
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135
Bit Position
Type
W1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Channel 7 Pulse Generation
Channel 6 Pulse Generation
Channel 5 Pulse Generation
Channel 4 Pulse Generation
Channel 3 Pulse Generation
Channel 2 Pulse Generation
Channel 1 Pulse Generation
Channel 0 Pulse Generation
Description
Description
Software Pulse Register
Software Level Register
I/O Routing Register
Channel Control Register
Channel Control Register
Channel Control Register
Channel Control Register
Channel Control Register
Channel Control Register
Channel Control Register
Channel Control Register
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