EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 420

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

25.5.15 DACn_OPAOFFSET - Operational Amplifier Offset Register
25.5.16 DACn_OPA0MUX - Operational Amplifier Mux Configuration
Register
11:9
8
7
6
5:3
2
1
0
31:6
5:0
Bit
Offset
0x058
Reset
Access
Name
Bit
Offset
0x05C
Reset
Access
Name
2010-12-21 - d0034_Rev0.90
Reserved
OPA2HCMDIS
Set to disable high common mode. Disables rail-to-rail on input, while output still remains rail-to-rail. The input voltage to the opamp
while HCM is disabled is restricted between VSS and VDD-1.2V.
OPA1HCMDIS
Set to disable high common mode. Disables rail-to-rail on input, while output still remains rail-to-rail. The input voltage to the opamp
while HCM is disabled is restricted between VSS and VDD-1.2V.
OPA0HCMDIS
Set to disable high common mode. Disables rail-to-rail on input, while output still remains rail-to-rail. The input voltage to the opamp
while HCM is disabled is restricted between VSS and VDD-1.2V.
Reserved
OPA2EN
Set to enable OPA2, clear to disable.
OPA1EN
Set to enable OPA1, clear to disable.
OPA0EN
Set to enable OPA0, clear to disable.
Reserved
OPA2OFFSET
This register contains the offset calibration value for OPA2. This field is set to the production OPA2 offset calibration value, hence
the reset value might differ from device to device. The field is sign-magnitude encoded. Higher values lead to lower OPA results.
The resolution of the LSB is 1.6mV/LSB
Name
Name
0
0
0
0
0
0
0x00
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
RW
Access
Access
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Bit Position
Bit Position
High Common Mode Disable.
High Common Mode Disable.
High Common Mode Disable.
OPA2 Enable
OPA1 Enable
OPA0 Enable
OPA2 Offset Configuration Value
Description
Description
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