EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 264
EFM32TG210F32
Manufacturer Part Number
EFM32TG210F32
Description
MCU 32BIT 32KB FLASH 32-QFN
Manufacturer
Energy Micro
Series
Tiny Geckor
Specifications of EFM32TG210F32
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.8 V
Data Converters
A/D 4x12b, D/A 1x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad
Processor Series
EFM32
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
UART, I2C, SPI
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
17
Number Of Timers
1
Operating Supply Voltage
1.8 V to 3.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Processor To Be Evaluated
EFM32TG210
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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17.5.6 TIMERn_IFS - Interrupt Flag Set Register
4
3:2
1
0
31:11
10
9
8
7
6
5
4
3:2
1
0
Bit
Offset
0x014
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
CC0
This bit indicates that there has been an interrupt event on Compare/Capture channel 0.
Reserved
UF
This bit indicates that there has been an underflow.
OF
This bit indicates that there has been an overflow.
Reserved
ICBOF2
Writing a 1 to this bit will set Compare/Capture channel 2 input capture buffer overflow interrupt flag.
ICBOF1
Writing a 1 to this bit will set Compare/Capture channel 1 input capture buffer overflow interrupt flag.
ICBOF0
Writing a 1 to this bit will set Compare/Capture channel 0 input capture buffer overflow interrupt flag.
Reserved
CC2
Writing a 1 to this bit will set Compare/Capture channel 2 interrupt flag.
CC1
Writing a 1 to this bit will set Compare/Capture channel 1 interrupt flag.
CC0
Writing a 1 to this bit will set Compare/Capture channel 0 interrupt flag.
Reserved
UF
Writing a 1 to this bit will set the underflow interrupt flag.
OF
Writing a 1 to this bit will set the overflow interrupt flag.
Name
Name
0
0
0
0
0
0
0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
R
R
R
W1
W1
W1
W1
W1
W1
W1
W1
Access
Access
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264
Bit Position
CC Channel 0 Interrupt Flag
Underflow Interrupt Flag
Overflow Interrupt Flag
CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Set
CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Set
CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Set
CC Channel 2 Interrupt Flag Set
CC Channel 1 Interrupt Flag Set
CC Channel 0 Interrupt Flag Set
Underflow Interrupt Flag Set
Overflow Interrupt Flag Set
Description
Description
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