EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 338

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

25:24
23:22
21:20
19
18
17:15
14:10
9:8
7:6
5:4
Bit
2010-12-21 - d0034_Rev0.90
Reserved
ACMP1MODE
Configure how LESENSE controls ACMP1
ACMP0MODE
Configure how LESENSE controls ACMP0
Reserved
DACREF
Set to BANDGAP if the DAC is configured to use bandgap reference
Reserved
DACPRESC
Prescaling factor of DACPRESC+1 for the LESENSE DAC interface
DACCH1OUT
DACCH0OUT
DACCH1CONV
Name
Value
0
1
2
3
Value
0
1
2
Value
0
1
2
Value
0
1
Value
0
1
2
3
Value
0
1
2
3
Value
0
1
2
Mode
NORMAL
KEEPACMPWARM
KEEPDACWARM
KEEPACMPDACWARM
Mode
DISABLE
MUX
MUXTHRES
Mode
DISABLE
MUX
MUXTHRES
Mode
VDD
BANDGAP
Mode
DISABLE
PIN
ADCACMP
PINADCACMP
Mode
DISABLE
PIN
ADCACMP
PINADCACMP
Mode
DISABLE
CONTINUOUS
SAMPLEHOLD
0x0
0x0
0
0x00
0x0
0x0
0x0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
RW
Access
Description
The analog comparators and DAC are shut down when LESENSE is idle
The analog comparators are kept powered up when LESENSE is idle
The DAC is kept powered up when LESENSE is idle
The analog comparators and DAC are kept powered up when LESENSE is idle
Description
LESENSE does not control ACMP1
LESENSE controls the input mux (POSSEL) of ACMP1
LESENSE controls the input mux and the threshold value (VDDLEVEL) of ACMP1
Description
LESENSE does not control ACMP0
LESENSE controls the input mux (POSSEL) of ACMP0
LESENSE controls the input mux (POSSEL) and the threshold value (VDDLEVEL) of
ACMP0
Description
DAC uses VDD reference
DAC uses bandgap reference
Description
DAC CH1 output to pin and ACMP/ADC disabled
DAC CH1 output to pin enabled, output to ADC and ACMP disabled
DAC CH1 output to pin disabled, output to ADC and ACMP enabled
DAC CH1 output to pin, ADC, and ACMP enabled.
Description
DAC CH0 output to pin and ACMP/ADC disabled
DAC CH0 output to pin enabled, output to ADC and ACMP disabled
DAC CH0 output to pin disabled, output to ADC and ACMP enabled
DAC CH0 output to pin, ADC, and ACMP enabled.
Description
LESENSE does not control DAC CH1.
DAC channel 1 is driven in continuous mode.
DAC channel 1 is driven in sample hold mode.
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338
ACMP1 mode
ACMP0 mode
DAC bandgap reference used
DAC prescaler configuration.
DAC channel 1 output mode
DAC channel 0 output mode
DAC channel 1 conversion mode
Description
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