EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 303

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

20.3.1 Pulse Counter Modes
20.3.1.1 Single Input Oversampling Mode
20.3.1.2 Externally Clocked Single Input Counter Mode
2010-12-21 - d0034_Rev0.90
Figure 20.1. PCNT Overview
The pulse counter can operate in single input oversampling mode (OVSSINGLE), externally clocked
single input counter mode (EXTCLKSINGLE) and externally clocked quadrature decoder mode
(EXTCLKQUAD). The following sections describe operation of each of the three modes and how they
are enabled. Input timing constraints are described in Section 20.3.5 (p. 306) and Section 20.3.6 (p.
306) .
This mode is enabled by writing OVSSINGLE (0x1) to the MODE field in the PCNTn_CTRL register and
disabled by writing DISABLE (0x0) to the same field. LFACLK is configured from the registers in the
Clock Management Unit (CMU), Chapter 11 (p. 94) .
The optional pulse width filter is enabled by setting to the FILT bit in the PCNTn_CTRL register.
Additionally, the PCNTn_S0IN input may be inverted, so that falling edges are counted, by setting to
the EDGE bit in the PCNTn_CTRL register.
If S1CDIR is cleared, PCNTn_S0IN is the only observed input in this mode. The PCNTn_S0IN input
is sampled by the LFACLK and the number of detected positive or negative edges on PCNTn_S0IN
appears in PCNTn_CNT. The counter may be configured to count down by setting to the CNTDIR bit
in PCNTn_CTRL. Default is to count up.
The counting direction can also be controlled externally in this mode by setting S1CDIR in PCNTn_CTRL.
This will make the input value on PCNTn_S1IN decide the direction counted on a PCNTn_S0IN edge.
If PCNTn_S1IN is high, the count is done according to CNTDIR in PCNTn_CTRL. If low, the count
direction is opposite.
This mode is enabled by writing EXTCLKSINGLE (0x2) to the MODE field in the PCNTn_CTRL register
and disabled by writing DISABLE (0x0) to the same field. The external pin clock source must be
configured from the registers in the CMU (Chapter 11 (p. 94) ).
Positive edges on PCNTn_S0IN are used to clock the counter. Similar to the oversampled mode,
PCNTn_S1IN is used to determine the count direction if S1CDIR in PCNTn_CTRL is set. If not, CNTDIR
in PCNTn_CTRL solely defines count direction. As the LFACLK is not used in this mode, the PCNT
module can operate in EM3.
S1PRS Input
S0PRS Input
CMU (conseptual)
Inverter
Inverter
LFACLK
Clock
switch
Pulse Width
Quadrature
decoder
Filter
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303
detector
Edge
EXTCLK_SINGLE
EXTCLK_QUAD
OVR_SINGLE
1
CNT
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TOP
Peripheral bus
TOPB