EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 498

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

29.5.4 LCD_BACTRL - Blink and Animation Control Register (Async Reg)
31:10
9:0
31:24
23:18
17:16
15:9
8
7
6:5
4:3
Bit
Offset
0x00C
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
For more information about Asynchronous Registers please see Section 5.3 (p. 18) .
Reserved
SEGEN
Determines which segment lines are enabled. Each bit represents a group of 4 segment lines. To enable segment lines X to X+3,
set bit X/4, i.e. to enable output on segment lines 4,5,6 and 7, set bit 1.
Reserved
FCTOP
These bits contain the Top Value for the Frame Counter: CLK
FCPRESC
These bits controls the prescaling value for the Frame Counter input clock.
Reserved
FCEN
When this bit is set, the frame counter is enabled.
ALOGSEL
When this bit is set, the animation registers are AND'ed together. When this bit is cleared, the animation registers are OR'ed together.
AREGBSC
These bits controls the shift operation that is performed on Animation register B.
AREGASC
These bits controls the shift operation that is performed on Animation register A.
Name
Name
Value
0
1
2
3
Value
0
1
Value
0
1
2
Value
0
1
Mode
DIV1
DIV2
DIV4
DIV8
Mode
AND
OR
Mode
NOSHIFT
SHIFTLEFT
SHIFTRIGHT
Mode
NOSHIFT
SHIFTLEFT
0x000
0x00
0x0
0
0
0x0
0x0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
RW
Access
Access
Description
CLK
CLK
CLK
CLK
Description
AREGA and AREGB AND'ed
AREGA and AREGB OR'ed
Description
No Shift operation on Animation Register B
Animation Register B is shifted left
Animation Register B is shifted right
Description
No Shift operation on Animation Register A
Animation Register A is shifted left
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498
Bit Position
FC
FC
FC
FC
EVENT
Segment Enable
Frame Counter Top Value
Frame Counter Prescaler
= CLK
= CLK
= CLK
= CLK
Frame Counter Enable
Animate Logic Function Select
Animate Register B Shift Control
Animate Register A Shift Control
Description
Description
FRAME
FRAME
FRAME
FRAME
= CLK
/ 1
/ 2
/ 4
/ 8
FC
/ (1 + FCTOP[5:0]).
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