EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 301

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

19.5.15 LETIMERn_ROUTE - I/O Routing Register
1
0
31:11
10:8
7:2
1
0
Bit
Offset
0x040
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
Set when the value written to LETIMERn_COMP0 is being synchronized.
CMD
Set when the value written to LETIMERn_CMD is being synchronized.
CTRL
Set when the value written to LETIMERn_CTRL is being synchronized.
Reserved
LOCATION
Decides the location of the LETIMER I/O pins
Reserved
OUT1PEN
When set, output 1 of the LETIMER is enabled
OUT0PEN
When set, output 0 of the LETIMER is enabled
Name
Name
Value
0
1
2
3
Value
0
1
Value
0
1
Mode
LOC0
LOC1
LOC2
LOC3
Description
The LETn_O1 pin is disabled
The LETn_O1 pin is enabled
Description
The LETn_O0 pin is disabled
The LETn_O0 pin is enabled
0
0
0x0
0
0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
R
R
RW
RW
RW
Access
Access
Description
Location 0
Location 1
Location 2
Location 3
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301
Bit Position
LETIMERn_CMD Register Busy
LETIMERn_CTRL Register Busy
I/O Location
Output 1 Pin Enable
Output 0 Pin Enable
Description
Description
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