EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 171
EFM32TG210F32
Manufacturer Part Number
EFM32TG210F32
Description
MCU 32BIT 32KB FLASH 32-QFN
Manufacturer
Energy Micro
Series
Tiny Geckor
Specifications of EFM32TG210F32
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.8 V
Data Converters
A/D 4x12b, D/A 1x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad
Processor Series
EFM32
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
UART, I2C, SPI
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
17
Number Of Timers
1
Operating Supply Voltage
1.8 V to 3.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Processor To Be Evaluated
EFM32TG210
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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14.5.15 I2Cn_ROUTE - I/O Routing Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
31:11
Bit
Offset
0x038
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
CLTO
Enable interrupt on clock low timeout.
BITO
Enable interrupt on bus idle timeout.
RXUF
Enable interrupt on receive buffer underflow.
TXOF
Enable interrupt on transmit buffer overflow.
BUSHOLD
Enable interrupt on bus-held.
BUSERR
Enable interrupt on bus error.
ARBLOST
Enable interrupt on loss of arbitration.
MSTOP
Enable interrupt on MSTOP.
NACK
Enable interrupt when not-acknowledge is received.
ACK
Enable interrupt on acknowledge received.
RXDATAV
Enable interrupt on receive buffer full.
TXBL
Enable interrupt on transmit buffer level.
TXC
Enable interrupt on transfer completed.
ADDR
Enable interrupt on recognized address.
RSTART
Enable interrupt on transmitted or received repeated START condition.
START
Enable interrupt on transmitted or received START condition.
Reserved
Name
Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Access
Access
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171
Bit Position
Clock Low Interrupt Enable
Bus Idle Timeout Interrupt Enable
Receive Buffer Underflow Interrupt Enable
Transmit Buffer Overflow Interrupt Enable
Bus Held Interrupt Enable
Bus Error Interrupt Enable
Arbitration Lost Interrupt Enable
MSTOP Interrupt Enable
Not Acknowledge Received Interrupt Enable
Acknowledge Received Interrupt Enable
Receive Data Valid Interrupt Enable
Transmit Buffer level Interrupt Enable
Transfer Completed Interrupt Enable
Address Interrupt Enable
Repeated START condition Interrupt Enable
START Condition Interrupt Enable
Description
Description
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