EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 313
EFM32TG210F32
Manufacturer Part Number
EFM32TG210F32
Description
MCU 32BIT 32KB FLASH 32-QFN
Manufacturer
Energy Micro
Series
Tiny Geckor
Specifications of EFM32TG210F32
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.8 V
Data Converters
A/D 4x12b, D/A 1x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad
Processor Series
EFM32
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
UART, I2C, SPI
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
17
Number Of Timers
1
Operating Supply Voltage
1.8 V to 3.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Processor To Be Evaluated
EFM32TG210
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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20.5.10 PCNTn_IEN - Interrupt Enable Register
20.5.11 PCNTn_ROUTE - I/O Routing Register
2
1
0
31:4
3
2
1
0
31:11
10:8
Bit
Offset
0x024
Reset
Access
Name
Bit
Offset
0x028
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
Write to 1 to clear the auxillary overflow interrupt flag
DIRCNG
Write to 1 to clear the direction change detect interrupt flag
OF
Write to 1 to clear the overflow interrupt flag
UF
Write to 1 to clear the underflow interrupt flag
Reserved
AUXOF
Enable the auxillary overflow interrupt
DIRCNG
Enable the direction change detect interrupt.
OF
Enable the overflow interrupt
UF
Enable the underflow interrupt
Reserved
LOCATION
Defines the location of the PCNT input pins. E.g. PCNTn_S0#0, #1 or #2.
Name
Name
Name
Value
0
Mode
LOC0
0
0
0
0
0
0
0
0x0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
W1
W1
W1
RW
RW
RW
RW
RW
Access
Access
Access
Description
Select location 0
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313
Bit Position
Bit Position
Direction Change Detect Interrupt Clear
Overflow Interrupt Clear
Underflow Interrupt Clear
Auxillary Overflow Interrupt Enable
Direction Change Detect Interrupt Enable
Overflow Interrupt Enable
Underflow Interrupt Enable
I/O Location
Description
Description
Description
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