EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 411

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

25.4 Register Map
25.5 Register Description
25.5.1 DACn_CTRL - Control Register
31:22
21:20
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x054
0x058
0x05C
0x060
0x064
Offset
0x000
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
The offset register address is relative to the registers base address.
Reserved
REFRSEL
Select refresh counter timeout value. A channel x will be refreshed with the interval set in this register if the REFREN bit in
DACn_CHxCTRL is set.
Name
Value
0
1
2
Name
DACn_CTRL
DACn_STATUS
DACn_CH0CTRL
DACn_CH1CTRL
DACn_IEN
DACn_IF
DACn_IFS
DACn_IFC
DACn_CH0DATA
DACn_CH1DATA
DACn_COMBDATA
DACn_CAL
DACn_BIASPROG
DACn_OPACTRL
DACn_OPAOFFSET
DACn_OPA0MUX
DACn_OPA1MUX
DACn_OPA2MUX
Mode
8CYCLES
16CYCLES
32CYCLES
0x0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
Access
Description
All channels with enabled refresh are refreshed every 8 prescaled cycles
All channels with enabled refresh are refreshed every 16 prescaled cycles
All channels with enabled refresh are refreshed every 32 prescaled cycles
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411
Bit Position
Type
RW
R
RW
RW
RW
R
W1
W1
RW
RW
W
RW
RW
RW
RW
RW
RW
RW
Refresh Interval Select
Description
Description
Control Register
Status Register
Channel 0 Control Register
Channel 1 Control Register
Interrupt Enable Register
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
Channel 0 Data Register
Channel 1 Data Register
Combined Data Register
Calibration Register
Bias Programming Register
Operational Amplifier Control Register
Operational Amplifier Offset Register
Operational Amplifier Mux Configuration Register
Operational Amplifier Mux Configuration Register
Operational Amplifier Mux Configuration Register
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