EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 165

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

14.5.5 I2Cn_CLKDIV - Clock Division Register
14.5.6 I2Cn_SADDR - Slave Address Register
8
7
6
5
4
3
2
1
0
31:9
8:0
Bit
Offset
0x010
Reset
Access
Name
Bit
Offset
0x014
Reset
Access
Name
2010-12-21 - d0034_Rev0.90
RXDATAV
Set when data is available in the receive buffer. Cleared when the receive buffer is empty.
TXBL
Indicates the level of the transmit buffer. Set when the transmit buffer is empty, and cleared when it is full.
TXC
Set when a transmission has completed and no more data is available in the transmit buffer. Cleared when a new transmission starts.
PABORT
An abort is pending and will be transmitted as soon as possible.
PCONT
A continue is pending and will be transmitted as soon as possible.
PNACK
A not-acknowledge is pending and will be transmitted as soon as possible.
PACK
An acknowledge is pending and will be transmitted as soon as possible.
PSTOP
A stop condition is pending and will be transmitted as soon as possible.
PSTART
A start condition is pending and will be transmitted as soon as possible.
Reserved
DIV
Specifies the clock divider for the I
Name
Name
0
1
0
0
0
0
0
0
0
0x000
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2
C. Note that DIV must be 1 or higher when slave is enabled.
R
R
R
R
R
R
R
R
R
RW
Access
Access
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165
Bit Position
Bit Position
RX Data Valid
TX Buffer Level
TX Complete
Pending abort
Pending continue
Pending NACK
Pending ACK
Pending STOP
Pending START
Clock Divider
Description
Description
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