EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 518

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2010-12-21 - d0034_Rev0.90
List of Tables
2.1. Register Access Types ............................................................................................................................ 3
3.1. Energy Mode Description ......................................................................................................................... 8
3.2. EFM32TG Microcontroller Family ............................................................................................................... 9
4.1. Interrupt Request Lines (IRQ) .................................................................................................................. 12
5.1. Memory System Core Peripherals ............................................................................................................ 15
5.2. Memory System Low Energy Peripherals ................................................................................................... 16
5.3. Memory System Peripherals .................................................................................................................... 17
5.4. Device Information Table ........................................................................................................................ 21
7.1. MSC Flash Memory Mapping .................................................................................................................. 29
7.2. Lock Bits Page Structure ........................................................................................................................ 29
7.3. Revision Number Interpretation ................................................................................................................ 30
8.1. AHB bus transfer arbitration interval ......................................................................................................... 46
8.2. DMA channel priority ............................................................................................................................. 46
8.3. DMA cycle types ................................................................................................................................... 48
8.4. channel_cfg for a primary data structure, in memory scatter-gather mode ......................................................... 51
8.5. channel_cfg for a primary data structure, in peripheral scatter-gather mode ...................................................... 53
8.6. Address bit settings for the channel control data structure ............................................................................. 56
8.7. src_data_end_ptr bit assignments ............................................................................................................ 57
8.8. dst_data_end_ptr bit assignments ............................................................................................................ 58
8.9. channel_cfg bit assignments ................................................................................................................... 58
8.10. DMA cycle of six words using a word increment ........................................................................................ 61
8.11. DMA cycle of 12 bytes using a halfword increment .................................................................................... 62
9.1. RMU Reset Cause Register Interpretation ................................................................................................. 82
10.1. EMU Energy Mode Overview ................................................................................................................. 89
10.2. EMU Entering a Low Energy Mode ......................................................................................................... 90
10.3. EMU Wakeup Triggers from Low Energy Modes ....................................................................................... 91
13.1. Reflex Producers ............................................................................................................................... 132
13.2. Reflex Consumers ............................................................................................................................. 133
14.1. I
14.2. I
14.3. I
14.4. I
14.5. I
14.6. I
14.7. I
14.8. I
14.9. I
14.10. I
15.1. USART Asynchronous vs. Synchronous Mode ........................................................................................ 175
15.2. USART Pin Usage ............................................................................................................................. 175
15.3. USART Data Bits ............................................................................................................................... 176
15.4. USART Stop Bits ............................................................................................................................... 176
15.5. USART Parity Bits ............................................................................................................................. 177
15.6. USART Oversampling ......................................................................................................................... 177
15.7. USART Baud Rates @ 4MHz Peripheral Clock ....................................................................................... 178
15.8. USART SPI Modes ............................................................................................................................ 190
15.9. USART I2S Modes ............................................................................................................................ 192
15.10. USART IrDA Pulse Widths ................................................................................................................. 197
16.1. LEUART Parity Bit ............................................................................................................................. 220
16.2. LEUART Baud Rates ......................................................................................................................... 221
17.1. TIMER Counter Response in X2 Decoding Mode ..................................................................................... 250
17.2. TIMER Counter Response in X4 Decoding Mode ..................................................................................... 250
17.3. TIMER Events ................................................................................................................................... 257
18.1. RTC Resolution Vs Overflow ............................................................................................................... 273
19.1. LETIMER Repeat Modes ..................................................................................................................... 282
19.2. LETIMER Underflow Output Actions ...................................................................................................... 287
20.1. PCNT QUAD Mode Counter Control Function ......................................................................................... 305
21.1. LESENSE scan configuration selection .................................................................................................. 319
21.2. LESENSE excitation pin mapping ......................................................................................................... 321
21.3. LESENSE decoder configuration .......................................................................................................... 330
21.4. LESENSE decoder configuration .......................................................................................................... 331
22.1. Bias Configuration .............................................................................................................................. 365
23.1. Bias Configuration .............................................................................................................................. 375
24.1. ADC Single Ended Conversion ............................................................................................................. 388
24.2. ADC Differential Conversion ................................................................................................................ 389
24.3. Oversampling Result Shifting and Resolution .......................................................................................... 389
24.4. ADC Results Representation ................................................................................................................ 390
24.5. Calibration Register Effect ................................................................................................................... 391
26.1. General Opamp Mode Configuration ..................................................................................................... 429
26.2. Voltage Follower Unity Gain Configuration .............................................................................................. 430
26.3. Inverting input PGA Configuration ......................................................................................................... 430
2
2
2
2
2
2
2
2
2
C Reserved I
C Clock Modes ............................................................................................................................... 145
C Interactions in Prioritized Order ....................................................................................................... 148
C Master Transmitter ........................................................................................................................ 150
C Master Receiver ........................................................................................................................... 152
C STATE Values ............................................................................................................................. 153
C Transmission Status ...................................................................................................................... 153
C Slave Transmitter ......................................................................................................................... 156
C - Slave Receiver .......................................................................................................................... 157
2
C Bus Error Response .................................................................................................................... 158
2
C Addresses ................................................................................................................ 143
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