EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 347
EFM32TG210F32
Manufacturer Part Number
EFM32TG210F32
Description
MCU 32BIT 32KB FLASH 32-QFN
Manufacturer
Energy Micro
Series
Tiny Geckor
Specifications of EFM32TG210F32
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.8 V
Data Converters
A/D 4x12b, D/A 1x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad
Processor Series
EFM32
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
UART, I2C, SPI
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
17
Number Of Timers
1
Operating Supply Voltage
1.8 V to 3.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Processor To Be Evaluated
EFM32TG210
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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21.5.16 LESENSE_ALTEXCONF - Alternative excite pin configuration
(Async Reg)
11:10
9:8
7:6
5:4
3:2
1:0
Bit
2010-12-21 - d0034_Rev0.90
For more information about Asynchronous Registers please see Section 5.3 (p. 18) .
CH5
CH4
CH3
CH2
CH1
CH0
Name
Value
0
1
2
Value
0
1
2
Value
0
1
2
3
Value
0
1
2
3
Value
0
1
2
3
Value
0
1
2
3
Mode
DISABLE
HIGH
LOW
Mode
DISABLE
HIGH
LOW
Mode
DISABLE
HIGH
LOW
DACCH0
Mode
DISABLE
HIGH
LOW
DACCH0
Mode
DISABLE
HIGH
LOW
DACCH0
Mode
DISABLE
HIGH
LOW
DACCH0
0x0
0x0
0x0
0x0
0x0
0x0
Reset
RW
RW
RW
RW
RW
RW
Access
Description
CH5 output is disabled in idle phase
CH5 output is high in idle phase
CH5 output is low in idle phase
Description
CH4 output is disabled in idle phase
CH4 output is high in idle phase
CH4 output is low in idle phase
Description
CH3 output is disabled in idle phase
CH3 output is high in idle phase
CH3 output is low in idle phase
CH3 output is connected to DAC CH0 output in idle phase
Description
CH2 output is disabled in idle phase
CH2 output is high in idle phase
CH2 output is low in idle phase
CH2 output is connected to DAC CH0 output in idle phase
Description
CH1 output is disabled in idle phase
CH1 output is high in idle phase
CH1 output is low in idle phase
CH1 output is connected to DAC CH0 output in idle phase
Description
CH0 output is disabled in idle phase
CH0 output is high in idle phase
CH0 output is low in idle phase
CH0 output is connected to DAC CH0 output in idle phase
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347
Channel 5 idlephase configuration
Channel 4 idlephase configuration
Channel 3 idlephase configuration
Channel 2 idlephase configuration
Channel 1 idlephase configuration
Channel 0 idlephase configuration
Description
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