EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 70

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8.7.10 DMA_CHREQMASKC - Channel Request Mask Clear Register
8.7.11 DMA_CHENS - Channel Enable Set Register
0
31:8
7
6
5
4
3
2
1
0
Bit
Offset
0x024
Reset
Access
Name
Bit
Offset
0x028
Reset
Access
Name
2010-12-21 - d0034_Rev0.90
Write to 1 to disable peripheral requests for this channel.
CH0REQMASKS
Write to 1 to disable peripheral requests for this channel.
Reserved
CH7REQMASKC
Write to 1 to enable peripheral requests for this channel.
CH6REQMASKC
Write to 1 to enable peripheral requests for this channel.
CH5REQMASKC
Write to 1 to enable peripheral requests for this channel.
CH4REQMASKC
Write to 1 to enable peripheral requests for this channel.
CH3REQMASKC
Write to 1 to enable peripheral requests for this channel.
CH2REQMASKC
Write to 1 to enable peripheral requests for this channel.
CH1REQMASKC
Write to 1 to enable peripheral requests for this channel.
CH0REQMASKC
Write to 1 to enable peripheral requests for this channel.
Name
Name
0
0
0
0
0
0
0
0
0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW1
W1
W1
W1
W1
W1
W1
W1
W1
Access
Access
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Bit Position
Bit Position
70
Channel 0 Request Mask Set
Channel 7 Request Mask Clear
Channel 6 Request Mask Clear
Channel 5 Request Mask Clear
Channel 4 Request Mask Clear
Channel 3 Request Mask Clear
Channel 2 Request Mask Clear
Channel 1 Request Mask Clear
Channel 0 Request Mask Clear
Description
Description
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