EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 324

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2010-12-21 - d0034_Rev0.90
Upon a state transition, LESENSE can generate a pulse on one or more of the decoder PRS channels.
Which channel to generate a pulse on is configured in the PRSACT bit field. If PRSCNT in DECCTRL
is set, count signals will be generated on decoder PRS channels 0 and 1 according to the PRSACT
configuration. In this mode, channel 0 will pulse each time a count event occurs while channel 1 indicates
the count direction, 1 being up and 0 being down. The count direction will be kept at its previous state
in between count events. The EFM32TG pulse counter may be used to keep track of events based on
these PRS outputs.
If SETIF is set, the DECODER interrupt flag will be set when the transition occurs. If INTMAP in
DECCTRL and SETIF is set, a transition from state x will set the CHx interrupt flag in addition to the
DECODER flag.
Setting CHAIN in STx_TCONFA enables the decoder to evaluate more than two possible transitions for
each state. If none of the transitions defined in STx_TCONFA or STx_TCONFB matches, the decoder
will jump to the next descriptor pair and evaluate the transitions defined there. The decoder uses two
LFACLK
will check that the sensor state has not changed if none of the defined transitions match. The DECERR
interrupt flag will be set if none of the transitions match and the sensor state has changed. Figure 21.7 (p.
324) illustrates state transitions. The "Generate PRS signals and set interrupt flag" blocks will perform
actions according to the configuration in STx_TCONFA and STx_TCONFB.
Figure 21.7. Decoder state transition evaluation
ST
ST
NEXTSTATE
i_
signals and set
i+ 1
signals and set
Generate PRS
NEXTSTATE
Generate PRS
TCONF
interrupt flag
interrupt flag
_TCONF
LESENSE
Ai+ 1
Ai
NEXTSTATE
signals and set
signals and set
Generate PRS
NEXTSTATE
Generate PRS
cycles for each descriptor pair to be evaluated. If ERRCHK in CTRL is set, the decoder
interrupt flag
interrupt flag
Y
Y
Bi+ 1
SENSORSTATE & ~ MASK
Bi
SENSORSTATE & ~ MASK
COMP
COMP
STATE
Ai+ 1
Ai
& ~ MASK
& ~ MASK
i
Ai
Ai+ 1
Y
Ai
Ai+ 1
=
SENSORSTATE & ~ MASK
N
=
Y
N
COMP
SENSORSTATE & ~ MASK
Bi+ 1
COMP
& ~ MASK
Bi
& ~ MASK
Y
Bi+ 1
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Bi+ 1
324
Y
Bi
=
N
Bi
CHAIN
=
N
i+ 1
CHAIN
= 1
i
= 1
Set DECERR
interrupt flag
N
N
Y
SENSORSTATE changed & &
ERRCHK= 1
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N