EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 492

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2010-12-21 - d0034_Rev0.90
Table 29.12. LCD Animation Shift Register
The two registers are either OR’ed or AND’ed to achieve the displayed animation pattern. This is
controlled by ALOGSEL in LCD_BACTRL as shown in Table 29.13 (p. 492) . In addition, the regular
segment data SEGD0[7:0] is OR’ed with the animation pattern to generate the resulting output.
Table 29.13. LCD Animation Pattern
Each state is displayed one CLK
LCD_STATUS, software can identify which state that is currently active in the state sequence. Note that
the shifting operation is performed on internal registers that are not accessible in SW (when reading
LCD_AREGA and LCD_AREGB, the data that was original written will also be read back). The SW must
utilize the knowledge about the current state (ASTATE) to calculate what is currently output. ASTATE is
cleared when LCD_AREGA or LCD_AREGB are updated with new values. See Table 29.14 (p. 492)
for an example.
Table 29.14. LCD Animation Example
AREGnSC, n = A
or B
00
01
10
11
ALOGSEL
0
1
ASTATE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
LCD_AREGA
11000000
01100000
01100000
00110000
00110000
00011000
00011000
00001100
00001100
00000110
00000110
00000011
00000011
10000001
10000001
11000000
Mode
NOSHIFT
SHIFTLEFT
SHIFTRIGHT
Reserved
Mode
AND
OR
EVENT
Description
No Shift operation
Animation register is shifted left (LCD_AREGA is shifted every odd state,
LCD_AREGB is shifted every even state)
Animation register is shifted right (LCD_AREGA is shifted every odd state,
LCD_AREGB is shifted every even state)
Reserved
Description
LCD_AREGA and LCD_AREGB are AND’ed together
LCD_AREGA and LCD_AREGB are OR’ed together
period, see Section 29.3.10 (p. 490) . By reading ASTATE in
LCD_AREGB
11000000
11000000
01100000
01100000
00110000
00110000
00011000
00011000
00001100
00001100
00000110
00000110
00000011
00000011
10000001
10000001
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492
Resulting Data
11000000
11100000
01100000
01110000
00110000
00111000
00011000
00011100
00001100
00001110
00000110
00000111
00000011
10000011
10000001
11000001
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