EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 310

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

20.5.3 PCNTn_STATUS - Status Register
20.5.4 PCNTn_CNT - Counter Value Register
31:2
1
0
31:1
0
31:16
15:0
Bit
Offset
0x008
Reset
Access
Name
Bit
Offset
0x00C
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
Reserved
LTOPBIM
This bit has no effect since TOPB is not buffered and it is loaded directly into TOP. For EFM32TG revisions A and B: Load
PCNTn_TOPB into PCNTn_TOP. Please see the device datasheet for a description on how to extract the chip revision.
LCNTIM
Load PCNTn_TOP into PCNTn_CNT on the next counter clock cycle.
Reserved
DIR
Current direction status of the counter. This bit is valid in EXTCLKQUAD mode only.
Reserved
CNT
Gives read access to the counter.
Name
Name
Name
Value
0
1
Mode
UP
DOWN
0
0
0
0x0000
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
W1
W1
R
R
Access
Access
Access
Description
Up counter mode (clockwise in EXTCLKQUAD mode with the NEDGE bit in
PCNTn_CTRL set to 0)
Down counter mode
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310
Bit Position
Bit Position
Load TOPB Immediately
Load CNT Immediately
Current Counter Direction
Counter Value
Description
Description
Description
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