EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 308

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

20.4 Register Map
20.5 Register Description
20.5.1 PCNTn_CTRL - Control Register (Async Reg)
31:16
15:14
13:12
11:10
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x038
0x03C
Offset
0x000
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
The offset register address is relative to the registers base address.
For more information about Asynchronous Registers please see Section 5.3 (p. 18) .
Reserved
AUXCNTEV
Selects whether the regular counter responds to up-count events, down-count events or both
Reserved
CNTEV
Selects whether the regular counter responds to up-count events, down-count events or both
Name
Value
0
1
2
3
Name
PCNTn_CTRL
PCNTn_CMD
PCNTn_STATUS
PCNTn_CNT
PCNTn_TOP
PCNTn_TOPB
PCNTn_IF
PCNTn_IFS
PCNTn_IFC
PCNTn_IEN
PCNTn_ROUTE
PCNTn_FREEZE
PCNTn_SYNCBUSY
PCNTn_AUXCNT
PCNTn_INPUT
Mode
NONE
UP
DOWN
BOTH
0x0
0x0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
Access
Description
Never counts
Counts up on up-count events
Counts up on down-count events
Counts up on both up-count and down-count events
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308
Bit Position
Type
RW
W1
R
R
R
RW
R
W1
W1
RW
RW
RW
R
RWH
RW
Controls when the auxillary counter counts
Controls when the counter counts
Description
Description
Control Register
Command Register
Status Register
Counter Value Register
Top Value Register
Top Value Buffer Register
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
Interrupt Enable Register
I/O Routing Register
Freeze Register
Synchronization Busy Register
Auxillary Counter Value Register
PCNT Input Register
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