EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 406

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

25.3 Functional Description
25.3.1 Conversions
25.3.1.1 Continuous Mode
25.3.1.2 Sample/Hold Mode
25.3.1.3 Sample/Off Mode
25.3.1.4 Conversion Start
2010-12-21 - d0034_Rev0.90
• Output to ADC
• Sine generation mode
• Optional high strength line driver
An overview of the DAC module is shown in Figure 25.1 (p. 406) .
Figure 25.1. DAC Overview
The DAC consists of two channels (Channel 0 and 1) with separate 12-bit data registers
(DACn_CH0DATA and DACn_CH1DATA). These can be used to produce two independent single ended
outputs or the channel 0 register can be used to drive both outputs in differential mode. The DAC supports
three conversion modes, continuous, sample/hold, sample/off.
In continuous mode the DAC channels will drive their outputs continuously with the data in the
DACn_CHxDATA registers. This mode will maintain the output voltage and refresh is therefore not
needed.
In sample/hold mode, the DAC cores converts data on a triggered conversion and then holds the output
in a sample/hold element. When not converting, the DAC cores are turned off between samples, which
reduces the power consumption. Because of output voltage drift the sample/hold element will only hold
the output for a certain period without a refresh conversion. The reader is referred to the electrical
characteristics for the details on the voltage drift.
In sample/off mode the DAC and the sample/hold element is turned completely off between samples,
tristating the DAC output. This requires the DAC output voltage to be held externally. The references
are also turned off between samples, which means that a new warm-up period is needed before each
conversion.
The DAC channel must be enabled before it can be used. When the channel is enabled, a conversion
can be started by writing to the DACn_CHxDATA register. These data registers are also mapped into
a combined data register, DACn_COMBDATA, where the data values for both channels can be written
simultaneously. Writing to this register will start all enabled channels.
1.25 V
2.5 V
VDD
CH0DATA
CH1DATA
REFSEL
Ch 0
Ch 1
...the world's most energy friendly microcontrollers
406
ADC and ACMP
DACn_OUT0
DACn_OUT1
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