EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 419

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

25.5.14 DACn_OPACTRL - Operational Amplifier Control Register
13:12
11:8
7
6
5:4
3:0
31:25
24
23
22
21:18
17:16
15:14
13:12
Bit
Offset
0x054
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
Set this bit to halve the bias current.
Reserved
OPA2BIASPROG
These bits control the bias current level.
Reserved
HALFBIAS
Set this bit to halve the bias current.
Reserved
BIASPROG
These bits control the bias current level.
Reserved
OPA2SHORT
Set to short the non-inverting and invering input.
OPA1SHORT
Set to short the non-inverting and invering input.
OPA0SHORT
Set to short the non-inverting and Invering Input.
Reserved
OPA2LPFDIS
Disables the low pass filter between pad and the positive and negative inputmux.
OPA1LPFDIS
Disables the low pass filter between pad and the positive and negative inputmux.
OPA0LPFDIS
Disables the low pass filter between pad and the positive and negative input mux.
Name
Name
Value
1
2
Value
1
2
Value
1
2
Mode
PLPFDIS
NLPFDIS
Mode
PLPFDIS
NLPFDIS
Mode
PLPFDIS
NLPFDIS
0x7
1
0x7
0
0
0
0x0
0x0
0x0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
RW
RW
RW
Access
Access
Description
Disables the LPF between positive pad and positive input.
Disables the LPF between negative pad and negative input.
Description
Disables the LPF between positive pad and positive input.
Disables the LPF between negative pad and negative input.
Description
Disables the LPF between positive pad and positive input.
Disables the LPF between negative pad and negative input.
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419
Bit Position
Bias Programming Value for OPA2
Half Bias Current
Bias Programming Value
Short the non-inverting and Invering Input.
Short the non-inverting and Invering Input.
Short the non-inverting and Invering Input.
Disables Low Pass Filter.
Disables Low Pass Filter.
Disables Low Pass Filter.
Description
Description
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