EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 423

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

21:19
18:14
13
12
11
10:8
7:6
5:4
3
2:0
Bit
2010-12-21 - d0034_Rev0.90
Reserved
OUTPEN
Set to enable output, clear to disable output
NPEN
Connects pad to the negative input mux
PPEN
Connects pad to the positive input mux
Reserved
RESINMUX
These bits selects the source for the input mux to the resistor ladder
Reserved
NEGSEL
These bits selects the source for the inverting input on OPA1
Reserved
POSSEL
These bits selects the source for the non-inverting input on OPA1
Name
Value
0
1
2
3
Value
0x01
0x02
0x04
0x08
0x10
Value
0
1
2
3
4
Value
0
1
2
3
Value
0
1
2
3
4
Mode
DISABLE
MAIN
ALT
ALL
Mode
OUT0
OUT1
OUT2
OUT3
OUT4
Mode
DISABLE
OPA0INP
NEGPAD
POSPAD
VSS
Mode
DISABLE
UG
OPATAP
NEGPAD
Mode
DISABLE
DAC
POSPAD
OPA0IN
OPATAP
0x00
0
0
0x0
0x0
0x0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
Access
Description
OPA0 output is disabled
Main OPA0 output to pin enabled
OPA0 alternative output enabled.
Main OPA0 output drives both main and alternative outputs.
Description
Alternate Output 0
Alternate Output 1
Alternate Output 2
Alternate Output 3
Alternate Output 4
Description
Set for Unity Gain
set for OPA0 input
Neg pad connected
Pos pad connected
VSS connected
Description
Input disabled
Unity Gain feedback path
Feedback resistor
Input from neg pad
Description
Input disabled
DAC as input
POS PAD as input
OPA0 as input
Resistor ladder as input
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423
OPA1 Output Enable Value
OPA1 Negative Pad Input Enable
OPA1 Positive Pad Input Enable
OPA1 Resistor Ladder Input Mux
OPA1 inverting Input Mux
OPA1 non-inverting Input Mux
Description
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