EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 77

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8.7.21 DMA_IEN - Interrupt Enable register
2
1
0
31
30:8
7
6
5
4
3
2
1
0
Bit
Offset
0x100C
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
CH2DONE
Write to 1 to clear the corresponding DMA channel complete interrupt flag.
CH1DONE
Write to 1 to clear the corresponding DMA channel complete interrupt flag.
CH0DONE
Write to 1 to clear the corresponding DMA channel complete interrupt flag.
ERR
Set this bit to enable interrupt on AHB bus error.
Reserved
CH7DONE
Write to 1 to enable complete intterrupt on this DMA channel. Clear to disable the interrupt.
CH6DONE
Write to 1 to enable complete intterrupt on this DMA channel. Clear to disable the interrupt.
CH5DONE
Write to 1 to enable complete intterrupt on this DMA channel. Clear to disable the interrupt.
CH4DONE
Write to 1 to enable complete intterrupt on this DMA channel. Clear to disable the interrupt.
CH3DONE
Write to 1 to enable complete intterrupt on this DMA channel. Clear to disable the interrupt.
CH2DONE
Write to 1 to enable complete intterrupt on this DMA channel. Clear to disable the interrupt.
CH1DONE
Write to 1 to enable complete intterrupt on this DMA channel. Clear to disable the interrupt.
CH0DONE
Write to 1 to enable complete intterrupt on this DMA channel. Clear to disable the interrupt.
Name
Name
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
W1
W1
W1
RW
RW
RW
RW
RW
RW
RW
RW
RW
Access
Access
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Bit Position
77
DMA Channel 2 Complete Interrupt Flag Clear
DMA Channel 1 Complete Interrupt Flag Clear
DMA Channel 0 Complete Interrupt Flag Clear
DMA Error Interrupt Flag Enable
DMA Channel 7 Complete Interrupt Enable
DMA Channel 6 Complete Interrupt Enable
DMA Channel 5 Complete Interrupt Enable
DMA Channel 4 Complete Interrupt Enable
DMA Channel 3 Complete Interrupt Enable
DMA Channel 2 Complete Interrupt Enable
DMA Channel 1 Complete Interrupt Enable
DMA Channel 0 Complete Interrupt Enable
Description
Description
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