EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 143

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

14.3.1.3 Addresses
14.3.1.4 10-bit Addressing
2010-12-21 - d0034_Rev0.90
Examples of I
143) . The identifiers used are:
• ADDR - Address
• DATA - Data
• S - Start bit
• Sr - Repeated start bit
• P - Stop bit
• W/R - Read(1)/Write(0)
• A - ACK
• N - NACK
Figure 14.5. I
Figure 14.6. I
Figure 14.7. I
I
the START-condition contains the address of the slave the master wants to contact. In the 7-bit address
space, several addresses are reserved. These addresses are summarized in Table 14.1 (p. 143) , and
include a General Call address which can be used to broadcast a message to all slaves on the I
Table 14.1. I
To address a slave using a 10-bit address, two bytes are required to specify the address instead of
one. The seven first bits of the first byte must then be 1111 0XX, where XX are the two most significant
bits of the 10-bit address. As with 7-bit addresses, the eight bit of the first byte determines whether the
master wishes to read from or write to the slave. The second byte contains the eight least significant
bits of the slave address.
When a slave receives a 10-bit address, it must acknowledge both the address bytes if they match the
address of the slave.
2
S
I
0000-000
0000-000
0000-001
0000-010
0000-011
0000-1XX
1111-1XX
1111-0XX
2
C supports both 7-bit and 10-bit addresses. When using 7-bit addresses, the first byte transmitted after
C Address
ADDR
2
2
S
C Reserved I
2
2
2
C transfers are shown in Figure 14.5 (p. 143) , Figure 14.6 (p. 143) , and Figure 14.7 (p.
C Single Byte Write to Slave
C Double Byte Read from Slave
C Single Byte Write, then Repeated Start and Single Byte Read
W
ADDR
A
S
2
C Addresses
R/W
0
1
X
X
X
X
X
X
R
DATA
ADDR
A
W
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DATA
A
143
A
Sr
DATA
ADDR
A
Description
General Call address
START byte
Reserved for the C-Bus format
Reserved for a different bus format
Reserved for future purposes
Reserved for future purposes
Reserved for future purposes
10 Bit slave addressing mode
DATA
R
A
A
P
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DATA
N
P
2
C-bus.
N
P