EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 222

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.3.4.2 Frame Transmission Control
2010-12-21 - d0034_Rev0.90
using LEUARTn_TXDATAX, the 9th bit written to LEUARTn_TXDATAX overrides the value in BIT8DV,
and alone defines the 9th bit that is transmitted if 9-bit frames are used.
If a write is attempted to the transmit buffer when it is not empty, the TXOF interrupt flag in LEUARTn_IF
is set, indicating the overflow. The data already in the buffer is in that case preserved, and no data is
written.
In addition to the interrupt flag TXC in LEUARTn_IF and the status flag TXC in LEUARTn_STATUS
which are set when the transmitter becomes idle, TXBL in LEUARTn_STATUS and the TXBL interrupt
flag in LEUARTn_IF are used to indicate the level of the transmit buffer. Whenever the transmit buffer
becomes empty, these flags are set high. Both the TXBL status flag and the TXBL interrupt flag are
cleared automatically when data is written to the transmit buffer.
The transmit buffer, including the TX shift register can be cleared by setting command bit CLEARTX in
LEUARTn_CMD. This will prevent the LEUART from transmitting the data in the buffer and shift register,
and will make them available for new data. Any frame currently being transmitted will not be aborted.
Transmission of this frame will be completed. An overview of the operation of the transmitter is shown
in Figure 16.3 (p. 222) .
Figure 16.3. LEUART Transmitter Overview
The transmission control bits, which can be written using LEUARTn_TXDATAX, affect the transmission
of the written frame. The following options are available:
• Generate break: By setting WBREAK, the output will be held low during the first stop-bit period to
• Disable transmitter after transmission: If TXDISAT is set, the transmitter is disabled after the frame
• Enable receiver after transmission: If RXENAT is set, the receiver is enabled after the frame has
The transmission control bits in the LEUART cannot tristate the transmitter. This is performed
automatically by hardware however, if AUTOTRI in LEUARTn_CTRL is set. See Section 16.3.7 (p. 227)
for more information on half duplex operation.
generate a framing error. A receiver that supports break detection detects this state, allowing it to be
used e.g. for framing of larger data packets. The line is driven high for one baud period before the next
frame is transmitted so the next start condition can be identified correctly by the recipient. Continuous
breaks lasting longer than an UART frame are thus not supported by the LEUART. GPIO can be used
for this. Note that when AUTOTRI in LEUARTn_CTRL is used, the transmitter is not tristated before
the high-bit after the break has been transmitted.
has been fully transmitted.
been fully transmitted. It is enabled in time to detect a start-bit directly after the last stop-bit has been
transmitted.
LEUn_TX
TXENS
Transm it shift register
d0-d8
control
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222
d0
d1
d2
TXDATA
d3
d4
TXDATAX
d5
d6
d7
BIT8DV
d8
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control
0
Transm it buffer