EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 83

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

9.3.4 RESETn pin Reset
9.3.5 Watchdog Reset
9.3.6 Lockup Reset
9.3.7 System Reset Request
9.3.8 EM4 Reset
9.3.9 EM4 Wakeup Reset
2010-12-21 - d0034_Rev0.90
Figure 9.3. RMU Brown-out Detector Operation
Forcing the RESETn pin low generates a reset of the EFM32TG. The RESETn pin includes an on-
chip pull-up resistor, and can therefore be left unconnected if no external reset source is needed. Also
connected to the RESETn line is a filter which prevents glitches from resetting the EFM32TG.
The Watchdog circuit is a timer which (when enabled) must be cleared by software regularly. If software
does not clear it, a Watchdog reset is activated. This functionality provides recovery from a software
stalemate. Refer to the Watchdog section for specifications and description. A Watchdog reset does not
reset the Debug Interface. This allows an active debug session to continue in case of a Watchdog reset.
A Cortex-M3 lockup is the result of the core being locked up because of an unrecoverable exception
following the activation of the processor’s built-in system state protection hardware.
A Cortex-M3 lockup gives immediate indication of seriously errant kernel software. This is the result of
the core being locked up due to an unrecoverable exception following the activation of the processor’s
built in system state protection hardware. For more information about the Cortex-M3 lockup conditions
see the ARMv7-M Architecture Reference Manual. The Lockup reset does not reset the Debug Interface.
Set the LOCKUPRDIS bit in the RMU_CTRL register in order to disable this reset source.
Software may initiate a reset (e.g. if it finds itself in a non-recoverable state). By asserting the
SYSRESETREQ in the Application Interrupt and Reset Control Register (write 0x05FA 0004), a reset is
issued. The SYSRESETREQ does not reset the Debug Interface.
Whenever the system goes down into EM4, the EM4RST bit is set. This bit must be cleared by software
after waking up from EM4.
Whenever the system is woken up from EM4 on a pin reset request, the EM4WURST bit is set. This bit
must be cleared by software after waking up from EM4.
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