EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 240

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.5.15 LEUARTn_IEN - Interrupt Enable Register
16.5.16 LEUARTn_PULSECTRL - Pulse Control Register (Async Reg)
31:11
10
9
8
7
6
5
4
3
2
1
0
Offset
0x038
Reset
Access
Name
Bit
Offset
0x03C
Reset
Access
Name
2010-12-21 - d0034_Rev0.90
For more information about Asynchronous Registers please see Section 5.3 (p. 18) .
Reserved
SIGF
Enable interrupt on signal frame.
STARTF
Enable interrupt on start frame.
MPAF
Enable interrupt on multi-processor address frame.
FERR
Enable interrupt on framing error.
PERR
Enable interrupt on parity error.
TXOF
Enable interrupt on TX overflow.
RXUF
Enable interrupt on RX underflow.
RXOF
Enable interrupt on RX overflow.
RXDATAV
Enable interrupt on RX data.
TXBL
Enable interrupt on TX buffer level.
TXC
Enable interrupt on TX complete.
Name
0
0
0
0
0
0
0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Access
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240
Bit Position
Bit Position
Signal Frame Interrupt Enable
Start Frame Interrupt Enable
Multi-Processor Address Frame Interrupt Enable
Framing Error Interrupt Enable
Parity Error Interrupt Enable
TX Overflow Interrupt Enable
RX Underflow Interrupt Enable
RX Overflow Interrupt Enable
RX Data Valid Interrupt Enable
TX Buffer Level Interrupt Enable
TX Complete Interrupt Enable
Description
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