EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 35

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.5.2 MSC_READCTRL - Read Control Register
7.5.3 MSC_WRITECTRL - Write Control Register
31:6
5
4
3
2:0
31:2
Offset
0x004
Reset
Access
Name
Bit
Offset
0x008
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
Reserved
ICCDIS
Set this bit to automatically disable caching of vector fetches and instruction fetches in interrupt context. Cache lookup will still be
performed in interrupt context. When set, the performance counters will not count when these types of fetches occur.
AIDIS
When this bit is set the cache is not automatically invalidated when a write or page erase is performed.
IFCDIS
Disable instruction cache for internal flash memory.
MODE
After reset, the core clock is 14 MHz from the HFRCO and the MODE field of MSC_READCTRL register is set to WS1. The reset
value is WS1 because the HFRCO may produce a frequency above 16 MHz before it is calibrated. WS1 or WS1SCBTP mode is
required for a frequency above 16 MHz. If software wants to set a core clock frequency above 16 MHz, this register must be set to
WS1 or WS1SCBTP before the core clock is switched to the higher frequency. When changing to a lower frequency, this register
can be set to WS0 or WS0SCBTP after the frequency transition has been completed. If the HFRCO is used as clock source, wait
until the oscillator is stable on the new frequency to avoid unpredictable behavior.
Reserved
Name
Name
Value
0
1
2
3
Mode
WS0
WS1
WS0SCBTP
WS1SCBTP
0
0
0
0x1
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
Access
Access
Description
Zero wait-states inserted in fetch or read transfers
One wait-state inserted for each fetch or read transfer. This mode is required for a core
frequency above 16 MHz.
Zero wait-states inserted with the Suppressed Conditional Branch Target Prefetch
(SCBTP) function enabled. SCBTP saves energy by delaying Cortex-M3 conditional
branch target prefetches until the conditional branch instruction is in the execute stage.
When the instruction reaches this stage, the evaluation of the branch condition is
completed and the core does not perform a speculative prefetch of both the branch
target address and the next sequential address. With the SCBTP function enabled,
one instruction fetch is saved for each branch not taken, with a negligible performance
penalty.
One wait-state access with SCBTP enabled.
...the world's most energy friendly microcontrollers
Bit Position
Bit Position
35
Interrupt Context Cache Disable
Automatic Invalidate Disable
Internal Flash Cache Disable
Read Mode
Description
Description
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