EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 415

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

25.5.5 DACn_IEN - Interrupt Enable Register
25.5.6 DACn_IF - Interrupt Flag Register
31:6
5
4
3:2
1
0
31:6
5
4
3:2
1
0
Offset
0x010
Reset
Access
Name
Bit
Offset
0x014
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
Reserved
CH1UF
Enable/disable channel 1 data underflow interrupt.
CH0UF
Enable/disable channel 0 data underflow interrupt.
Reserved
CH1
Enable/disable channel 1 conversion complete interrupt.
CH0
Enable/disable channel 0 conversion complete interrupt.
Reserved
CH1UF
Indicates channel 1 data underflow.
CH0UF
Indicates channel 0 data underflow.
Reserved
CH1
Indicates channel 1 conversion complete.
CH0
Indicates channel 0 conversion complete.
Name
Name
0
0
0
0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
R
R
R
R
Access
Access
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415
Bit Position
Bit Position
Channel 1 Conversion Data Underflow Interrupt Enable
Channel 0 Conversion Data Underflow Interrupt Enable
Channel 1 Conversion Complete Interrupt Enable
Channel 0 Conversion Complete Interrupt Enable
Channel 1 Data Underflow Interrupt Flag
Channel 0 Data Underflow Interrupt Flag
Channel 1 Conversion Complete Interrupt Flag
Channel 0 Conversion Complete Interrupt Flag
Description
Description
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