EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 209

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.5.14 USARTn_TXDATA - TX Buffer Data Register
15.5.15 USARTn_TXDOUBLEX - TX Buffer Double Data Extended Register
13
12
11
10:9
8:0
31:8
7:0
31
30
Bit
Offset
0x034
Reset
Access
Name
Bit
Offset
0x038
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
Set to disable transmitter and release data bus directly after transmission.
TXBREAK
Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the value
of WDATA.
TXTRIAT
Set to tristate transmitter by setting TXTRI after transmission.
UBRXAT
Set clear RXBLOCK after transmission, unblocking the receiver.
Reserved
TXDATAX
Use this register to write data to the USART. If TXEN is set, a transfer will be initiated at the first opportunity.
Reserved
TXDATA
This frame will be added to TX buffer. Only 8 LSB can be written using this register. 9th bit and control bits will be cleared.
RXENAT1
Set to enable reception after transmission.
TXDISAT1
Name
Name
Name
0
0
0
0x000
0x00
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
W
W
W
W
W
W
W
Access
Access
Access
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209
Bit Position
Bit Position
Transmit Data As Break
Set TXTRI After Transmission
Unblock RX After Transmission
TX Data
TX Data
Enable RX After Transmission
Clear TXEN After Transmission
Description
Description
Description
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