EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 49

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8.4.2.3.4 Ping-pong
2010-12-21 - d0034_Rev0.90
3. The controller sets dma_done[C] HIGH for one HFCORECLK cycle. This indicates to the host
In ping-pong mode, the controller performs a DMA cycle using one of the data structures and it then
performs a DMA cycle using the other data structure. The controller continues to switch from primary to
alternate to primary… until it reads a data structure that is invalid, or until the host processor disables
the channel.
Figure 8.3 (p. 49) shows an example of a ping-pong DMA transaction.
Figure 8.3. Ping-pong example
In Figure 8.3 (p. 49) :
Task A
Task A: Prim ary, cycle_ctrl = b011, 2
Task B: Alternate, cycle_ctrl = b011, 2
Task C: Prim ary, cycle_ctrl = b011, 2
Task D: Alternate, cycle_ctrl = b011, 2
Task E: Prim ary, cycle_ctrl = b011, 2
End: Alternate, cycle_ctrl = b000
processor that the DMA cycle is complete.
1. The host processor configures the primary data structure for task A.
2. The host processor configures the alternate data structure for task B. This enables the
3. The controller receives a request and performs four DMA transfers.
4. The controller arbitrates. After the controller receives a request for this channel, the flow
5. The controller performs the remaining two DMA transfers.
controller to immediately switch to task B after task A completes, provided that a higher
priority channel does not require servicing.
continues if the channel has the highest priority.
Request
Request
Request
Request
Request
R
R
R
R
= 4, N = 7
= 4, N = 6
= 2, N = 2
R
Request
Request
Request
Request
Request
= 4, N = 12
= 4, N = 5
Task A
Task C
Task E
Task B
Task D
Invalid
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