mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1041

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

19.3.8 Video Frame Configuration Register (Set 1)
The video frame configuration register set 1 (VFCR1) has the same structure as VFCR0,
except it belongs to set 1 and VFCR0 belongs to set 0. The value of the VPC1 and NBPL1
fields must be non-zero or an error will occur.
SFB1—Single Frame Buffer 1
This bit controls whether the video controller displays an image from a single frame buffer
(A) or from both frame buffers (A and B).
Bits 1–2—Reserved
These bits are reserved and must be set to 0.
VPC1—Vertical Pixel Count 1
This field defines the number of lines for a field.
GAP1—Gap 1
This field defines the gap in the memory between the end of a line and the beginning of the
next line in full burst units. For regular noninterlace mode, this field is set to 0. For regular
interlace mode, it is set to the value in the NBPL1 field. For example, hardware pan/scroll
options in a zoomed buffer can be implemented by using the GAP1 field with an appropriate
field buffer start address.
NBPL1—Number of Bursts per Line 1
This field defines the number of bursts per line.
VFCR1
RESET
RESET
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
0 = Frame B is valid.
1 = Frame B is not valid.
SFB1 RESERVED
R/W
16
0
0
17
1
R/W
0
18
2
Freescale Semiconductor, Inc.
For More Information On This Product,
19
3
GAP1
R/W
0
20
MPC823 REFERENCE MANUAL
4
Go to: www.freescale.com
21
5
(IMMR & 0xFFFF0000) + 0x81C
(IMMR & 0xFFFF0000) + 0x81E
22
6
23
7
VPC1
R/W
0
24
8
25
9
10
26
11
27
NBPL1
R/W
0
12
28
Video Controller
13
29
GAP1
R/W
14
30
0
19-13
15
31