mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 97

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Reset
4.3.1.1 HARD RESET CONFIGURATION WORD. The hard reset configuration word is
sampled from the data bus. At reset, the bits will determine the default values of the
corresponding bits in the SIUMCR, IMMR, and MSR.
EARB—External Arbitration
If this bit is set (1), external arbitration is assumed. If it is cleared (0), then internal arbitration
is performed. See Section 12 System Interface Unit for more information.
IIP—Initial Interrupt Prefix
This bit defines the initial value of the MSR
the interrupt table location. If IIP is zero (default), the MSR
sampled one, the MSR
Bits 2, 6, and 15—Reserved
These bits are reserved and must be left open.
BDIS—Boot Disable
BPS—Boot Port Size
This field defines the port size of the boot device.
HARD RESET CONFIGURATION WORD
NOTE: The default value is due to the internal pull-down resistor on the data bus.
DEFAULT
DEFAULT
FIELD
FIELD
BIT
BIT
0 = The memory controller is activated after reset so that it matches all addresses.
1 = The memory controller is not activated after reset, but it is cleared.
00 = 32-bit port size.
01 = 8-bit port size.
10 = 16-bit port size.
11 = Reserved.
EARB
16
0
0
IIP
17
1
0
RES
18
2
0
IP
Freescale Semiconductor, Inc.
BDIS
initial value is zero.
For More Information On This Product,
19
3
0
20
MPC823 REFERENCE MANUAL
4
BPS
0
Go to: www.freescale.com
21
5
RES
22
6
0
IP
immediately after reset. The MSR
RESERVED
23
7
ISB
0
0
24
8
25
9
DBGC
IP
0
initial value is one, but if it is
10
26
11
27
DBPC
0
12
28
13
29
IP
EBDF
0
bit defines
MOTOROLA
14
30
RES
15
31
0