mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 909

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

16.13.3.1.2 Master Read. To begin a read operation to a slave device that contains internal
addresses, you must prepare two TX buffers. TX buffer 0 must be 2 bytes long and TX buffer
1 must be N+1 bytes long, where N is the number of bytes to be read sequentially from the
slave device. You must also prepare one or more receive buffers for the N bytes of data to
receive from the slave device.
The first byte of TX buffer 0 must contain the 7-bit slave address followed by the write bit
asserted (R/W = 0). The second byte of the first transmit buffer must contain the 1-byte
internal address on the slave device. This is the base address on the slave device of the
data to be read. The transmission of TX buffer 0 is commonly referred to as a dummy write.
Its purpose is to select the slave device.
The first byte of the second TX buffer (1) must contain the slave address followed by the
read bit asserted (R/W = 1). The remaining N bytes of TX buffer 1 may be uninitialized and
merely serve as a placeholder for the I
TX buffer descriptor.
To begin a read operation to a slave device that does not contain internal addresses, you
must prepare a TX buffer of N+1 bytes long, where N is the number of bytes to be read
sequentially from the slave device. The first byte of the TX buffer must contain the 7-bit slave
address followed by the read bit asserted (R/W = 1). You must also prepare one or more
receive buffers for the N bytes of data to receive from the slave device.
SDA
NOTE: DATA AND ACK ARE REPEATED N TIMES.
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Figure 16-129. Byte Read from Device without Internal Addresses
Figure 16-128. Byte Read from Device with Internal Addresses
SDA
NOTE: DATA AND ACK ARE REPEATED N TIMES.
DEVICE ADDR
Freescale Semiconductor, Inc.
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For More Information On This Product,
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MPC823 REFERENCE MANUAL
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DEVICE ADDR
Go to: www.freescale.com
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C controller. The W, L and S bits must be set in the
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DEVICE ADDR
DATA BYTE
Communication Processor Module
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DATA BYTE
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16-457
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