mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 203

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

LRU bits are updated. Therefore, in the simple case of the debug routine it is read from
memory like any other miss. However, for performance reasons, it might be preferable to
run the debug routine from the cache. Follow these steps with little variation:
After the debug routine has completed, the old state of the instruction cache can be restored
by following these steps:
9.9.1 Fetching Instructions From The Development Port
When the MPC823 is in debug mode, all instructions are fetched from the development port,
regardless of the address generated by the MPC823 core. Therefore, the instruction cache
is practically bypassed when the MPC823 is in debug mode.
1. Save both ways of the sets that are needed for the debug routine by reading the tag,
2. Unlock the locked ways in the selected sets.
3. Use a LOAD & LOCK command to load and lock the debug routine into the instruction
4. Run the debug routine. All accesses to it will result in hits.
1. Unlock and invalidate all the sets that are used by the debug routine (both ways).
2. Use a LOAD & LOCK command to restore the old sets.
3. Unlock the ways that were not previously locked.
4. To restore the old state of the LRU, the last access must be made in the MRU way. An
LRU code bit, valid bit, and lock bit values.
cache (LOAD & LOCK operates the same when FRZ is asserted).
access in this description is either LOAD & LOCK or UNLOCK LINE.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
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Instruction Cache
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