mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 333

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Table 13-3 lists the patterns of the data transfer for write cycles when accesses are initiated
by the MPC823.
13.4.6 Arbitration Phase-Related Signals
The external bus design provides for a single bus master, either the MPC823 or an external
device. One or more of the external devices on the bus has the capability of becoming bus
master for the external bus. Bus arbitration may be handled either by an external central bus
arbiter or by the internal on-chip arbiter. In the latter case, the system is optimized for one
external bus master besides the MPC823. The arbitration configuration (external or internal)
is set at system reset. See Section 15.6 External Master Support for more information.
Each bus master must have BR, BG, and BB signals. The device that needs the bus asserts
the BR signal. The device then waits for the arbiter to assert the BG signal. In addition, the
new master must look at the BB signal to ensure that no other master is driving the bus
before it can assert BB and assume ownership of the bus. If the arbiter has taken the BG
away from the master and the master wants to execute a new cycle, the master must
rearbitrate before a new cycle can be initiated. The MPC823, however, guarantees data
coherency for burst accesses to a small port size. This means that the MPC823 will not
release the bus until the transactions (atomic) complete.
Byte
Half-Word
Word
NOTE: — Denotes that a byte is not required during that write cycle.
TRANSFER
SIZE
Table 13-3. Data Bus Contents for Write Cycles
0
0
0
0
1
1
0
TSIZE
[0:1]
Freescale Semiconductor, Inc.
For More Information On This Product,
1
1
1
1
0
0
0
INTERNAL
A30
ADDRESS
0
0
1
1
0
1
0
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
A31
0
1
0
1
0
0
0
D0–D7
OP0
OP1
OP2
OP3
OP0
OP2
OP0
EXTERNAL DATA BUS PATTERN
D8–D15
OP1
OP3
OP1
OP3
OP1
—
—
D16–D23
OP2
OP2
OP2
—
—
—
—
External Bus Interface
D24–D31
OP3
OP3
OP3
—
—
—
—
13-27