mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 236

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

11.6.1.4 MMU INSTRUCTION EFFECTIVE PAGE NUMBER REGISTER. The MMU
instruction effective page number (MI_EPN) register contains the effective address to be
loaded into a TLB entry.
EPN—Effective Page Number for the TLB Entry
This field is the effective address default value of the last instruction TLB miss.
Bits 20–21 and 23–27—Reserved
These bits are reserved and must be set to 0. Ignores on write and returns a 0 on read.
EV—TLB Entry Valid Bit
This bit is set to 1 on every instruction TLB miss.
ASID—Address Space ID
This field represent the address space ID of the instruction TLB entry to be compared with
the CASID field of the M_CASID register.
MI_EPN
NOTE: — = Undefined.
RESET
RESET
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
0 = The TLB entry is invalid.
1 = The TLB entry is valid.
16
0
17
1
EPN
R/W
—
18
2
Freescale Semiconductor, Inc.
For More Information On This Product,
19
3
RESERVED
20
MPC823 REFERENCE MANUAL
4
—
R
Go to: www.freescale.com
21
5
R/W
EV
22
6
0
23
SPR 787
SPR 787
7
EPN
R/W
0
24
8
RESERVED
25
R
9
0
10
26
11
27
Memory Management Unit
12
28
13
29
ASID
R/W
0
14
30
11-19
15
31