mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1337

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Index
R
raindrop effect,
RAM addresses, serial interface RAM,
RAM array and signal generation (illustration),
RAM array size,
RAM array, indexing service requests,
RAM word (definition),
RAM word format,
RAM word operation,
RAM words, storing,
RAM, video control,
RBS (definition),
RCCR,
RCLK,
RD/WR,
read accesses, extending hold time,
read hit,
read miss,
real-time alarm register key,
real-time alarm seconds key,
real-time clock alarm register,
real-time clock alarm seconds register,
real-time clock block diagram,
real-time clock register key,
real-time clock register,
real-time clock status and control register key,
real-time clock status and control register,
real-time clock,
reference bit updates,
register
register unit, of the core,
registers
48
universal serial bus status,
baud rate generator configuration,
boundary scan,
breakpoint address,
breakpoint counter A value and control,
breakpoint counter B value and control,
comparator A-D value,
comparator E-F value,
comparator G-H value,
condition,
control,
CPM command,
CPM interrupt controller,
data cache (special),
data cache address,
data cache control and status,
data synchronization,
debug enable,
decrementer,
development port data,
development port shift,
DSP event,
16-318
16-7
10-10
2-2
10-10
6-16
,
13-4
6-22
18-3
12-17
16-33
15-48
15-41
12-13
,
15-49
20-57
13-32
21-4
19-16
15-43
16-9
15-54
11-4
15-49
12-19
20-44
6-15
10-7
10-4
16-174
20-43
20-42
20-44
20-30
20-60
5-27
Freescale Semiconductor, Inc.
5-27
16-503
5-27
12-21
12-17
For More Information On This Product,
16-374
10-5
MPC823 REFERENCE MANUAL
15-34
15-42
16-157
16-123
12-20
Go to: www.freescale.com
12-18
20-53
20-54
15-
5-27
DSP mask,
fixed-point exception cause,
frame buffer A start address set 0,
frame buffer A start address,
frame buffer B start address,
general SCCx mode high and low,
general SMC mode,
I2C address,
I2C baud rate generator,
I2C command,
I2C event,
I2C mask,
I2C mode,
IDMA1 and 2 mask,
IDMA1 and 2 status,
instruction cache address,
instruction cache control and status,
instruction cache data port,
instruction support control,
internal memory map,
interrupt cause,
key,
LCD controller configuration,
load/store support AND-OR control,
load/store support comparators control,
machine A mode,
machine B mode,
machine state,
memory address,
memory command,
memory controller base,
memory controller option,
memory controller,
memory data,
memory periodic timer prescaler,
memory status,
MMU current addresss space ID,
MMU data access protection,
MMU data CAM entry read,
MMU data control,
MMU data effective page number,
MMU data RAM entry read 0,
MMU data RAM entry read 1,
MMU data real page number,
MMU data tablewalk control,
MMU instruction access protection,
MMU instruction CAM entry read,
MMU instruction control,
MMU instruction effective page number,
MMU instruction RAM entry read 0,
MMU instruction RAM entry read 1,
MMU instruction real page number,
MMU instruction tablewalk control,
MMU tablewalk base,
MMU tablewalk special,
3-4
,
5-27
16-473
16-472
16-465
16-34
16-470
15-26
16-471
6-20
15-15
20-55
15-26
15-19
15-22
11-17
15-7
15-17
16-95
16-381
16-94
11-36
3-1
11-37
15-9
11-16
16-471
,
15-11
,
9-6
20-45
12-34
,
9-7
16-110
11-38
16-109
6-23
11-34
18-26
18-27
18-20
11-32
11-39
11-41
11-26
MOTOROLA
15-27
11-18
11-43
11-20
19-11
16-163
11-33
11-31
11-45
11-46
11-21
20-50
9-5
20-48
11-19