mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 682

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
Communication Processor Module
16.9.16 The SCCs In HDLC Mode
Layer 2 of the seven-layer open systems interconnection model from ISO is the data link
layer and one of the most common protocols in this layer is high-level data link control
(HDLC). In fact, many other common layer 2 protocols—SDLC, SS#7, AppleTalk, LAPB,
and LAPD—are based on HDLC and its framing structure, which is illustrated
in Figure 16-76.
HDLC uses a zero insertion/deletion process (referred to as bit-stuffing) to ensure that the
bit pattern of the delimiter flag does not occur in the fields between flags. The HDLC frame
is synchronous and relies on the physical layer to provide a method for clocking and
synchronizing the transmitter/receiver.
Since the layer 2 frame can be transmitted over a point-to-point link, a broadcast network,
or packet and circuit switched systems, an address field is needed to carry the frame's
destination address. The length of this field is commonly 0, 8, or 16 bits, depending on the
data link layer protocol. For instance, SDLC and LAPB use an 8-bit address and SS#7 has
no address field at all because it is always used in point-to-point signaling links. LAPD
further divides its 16-bit address into different fields to specify various access points within
one piece of equipment. It also defines a broadcast address. Some HDLC-type protocols
allow for extended addressing beyond 16 bits.
The 8- or 16-bit control field provides a flow control number and defines the frame type
(control or data). The exact use and structure of this field depends on the protocol using the
frame. Data is transmitted in the data field and its length is dependent on the protocol of the
frame. Layer 3 frames are carried in this data field. Error control is implemented by
appending a cyclic redundancy check (CRC) to the frame, which in most protocols is 16 bits
long but can be as long as 32 bits. In HDLC, the least-significant bit of each octet is
transmitted first and the most-significant bit of the CRC is transmitted first.
When the MODE field of the GSMR_L is set to HDLC mode, a serial communication
controller is functioning in HDLC mode. When you use an SCCx in HDLC mode with a
nonmultiplexed modem interface, the serial communication controller outputs are connected
directly to the external pins. Modem signals can be supported through the port B and C pins.
The receive and transmit clocks can be supplied from either the bank of baud rate
generators, by the DPLL, or externally. You can also connect the SCCx in HDLC mode to
the TDM channel of the serial interface and use it with the time-slot assigner. The SCCx in
HDLC mode, also called the SCCx HDLC controller, consists of separate transmit and
receive sections whose operations are asynchronous with the core. You can allocate up to
196 buffer descriptors, so that you can transmit or receive many frames without interference
from the host.
MPC823 REFERENCE MANUAL
MOTOROLA
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