mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 337

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

13.4.7 Address Transfer Phase-Related Signals
13.4.7.1 TRANSFER START SIGNAL. The TS signal indicates the beginning of a cycle
initiated by the bus master. This signal must be asserted by a master only after ownership
of the bus is granted by the arbitration protocol. This signal is only asserted for the first clock
cycle of the transaction and is negated in the successive clock cycles. The master must
three-state this signal when it relinquishes the bus to avoid contention between two or more
masters in this signal. This configuration requires an external pull-up resistor to be
connected to the TS signal. This will prevent a slave from responding to a bogus TS
assertion. Refer back to Figure 13-21 for more information.
BR = 1
MPC823 NO LONGER
NEEDS THE BUS
THE EXTERNAL DEVICE THAT
HAS A HIGHER PRIORITY THAN
THE CURRENT INTERNAL BUS
MASTER REQUESTS THE BUS
BG = 1
BB = T.S
Figure 13-23. Internal Bus Arbitration State Machine
IDLE
EXT MASTER
REQUESTS BUS
BR = 0
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
MPC823 NEEDS
THE BUS
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EXT MASTER
RELEASE BUS
MPC823 OWNER
EXT OWNER
BG = 1
BB = 0
BG = 0
BB = T.S
MPC823 INTERNAL MASTER WITH HIGHER
PRIORITY THAN THE EXTERNAL DEVICE
REQUIRES THE BUS
MPC823 STILL NEEDS
THE BUS
BB = 1
MPC823 BUS WAIT
BG = 1
BB = T.S
External Bus Interface
BB = 0
13-31